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is25lp032/064 32m - bit/ 64m - bit 3v - multi i/o serial fla sh memory with 133mh z spi bus & quad i/o (qpi) dtr i nterface data sheet
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 2 rev. 0a 4/03/2014 features ? industry standard serial interface - is25lp 064:64m - bit/ 8 m - byte - is25lp 032:32m - bit/ 4 m - byte - 256 - bytes per programmable page - supports standard spi, fast, dual, dual i/o, qpi, dtr, dual dtr i/o, and qpi dtr spi - supports serial flash discoverable parameters (sfdp) ? high performance serial flash (spi) - 50mhz normal and 133mhz fast read - 532 mhz equivalent qpi spi - dtr (dual transfer rate) up to 66mhz - selectable dummy cycles - configurable drive strength - supports spi modes 0 and 3 - more than 100,000 erase/program cycles - more than 20 - year data retention ? flexible & efficient memory architecture - chip erase:128mbit with uniform: sector/blo c k era s e (4k/32k/6 4 k - byte) - prog r am 1 to 256 by t es per page - program/erase s u s pend & re s ume ? efficient read and program modes - low instruction overhead operations - continuous read 8/16/32/64 - b y te w r ap - selectable burst length - qpi for re d u c ed instru c tion overhe a d - allows xip operations (execute in place) ? low power with wide temp. ranges - single 2.3v to 3.6v voltage supply - 10 ma active read current - 5 a standby current - deep power down - temp grades: extended: - 40c to +105c auto grade: up to +125c (call factory) ? advanced security protection - software and hardware write protection - power supply lock protect - 4x256 - byte dedicated security area with user - lockable bits, (otp) one time programmable memory - 128 bit unique id for each device ? industry standard pin - out & packages - jm = 16 - pin soic 300mil - jb = 8 - pin soic 208mil - jf = 8 - pin vsop 208mil - jk = 8 - pin wson 6x5mm - jl = 8 - pin wson 8x6mm - kgd (call factory) 32 m - bit / 64 m - bit 3v - multi i/o serial fla sh memory with 133mh z spi bus & quad i/o (qpi) dtr i nterface
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 3 rev. 0a 4/03/2014 gen e r a l d e s c rip t i o n the is25lp032/064 serial flash memory offers a storage solution with the flexibility and performance in a simplified pin count package. issis industry standard serial interface flash are for systems that have limited space, pins, and power. the is25lp128 are accessed th rough a 4 - wire spi interface consisting of a serial data input (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins, which also serve as multi - function i/o (see pin descriptions). the device supports the standard serial periphera l interface (spi), dual/quad output (spi), and dual/quad i/o (spi). clock frequencies of up to 133mhz allow for equivalent clock rates of up to 532mhz (133mhz x 4) allowing more than 66mbytes/s of throughput. the is25xp series of flash adds support for dtr ( double transfer rate ) commands that transfer address and read data on both edges of the clock. these transfer rates can outperform 16 - bit parallel flash memories allowing for efficient memory access for a xip (execute in place) operation. the memory ar ray is organized into programmable pages of 256 - bytes each. the is25lp128 supports page program mode where 1 to 256 bytes of data can be programmed into the memory with one command. qpi (quad peripheral interface) supports 2 - cycles instruction cycles furth er reducing instruction times. pages can be erased in groups of 4k - byte sectors, 32k - byte blocks, 64k - byte blocks, and/or the entire chip. the uniform sectors and blocks allow greater flexibility for a variety of applications requiring solid data retention . glossary standard spi the is25 lp 032/064 is accessed through a 4 - wire spi interface consisting of serial data input (sl), serial data output (so), serial clock (sck), and chip enable (ce#) pins. instruction s are inputted through the si pin to encode instruction s , addresses, or input data to the device on the rising edge of sck. the do pin is used to r ead data or check the status of the device on the falling edge of sck. this d evice supports spi bus operation mode (0,0) and (1,1). mutil i/o spi the is25 lp 032/064 allows accessing enhanced spi protocol to use dual output, dual input and output, and quad input and output operation. executing these instruction s through spi mode will achieve double or quadruple the transfer bandwidth for read and program. quad i/o ( q pi ) the is25 lp 032/064 can enable qpi protocol by issuing an enter qpi mode (35h) command . the qpi mode uses four io pins for input and output to reduce spi instruction overhead and increase output bandwidth. qpi mode can exit by issuing an exit qpi (f5h) command. a power reset or software reset can also return the device into the standard spi mode. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode. dtr in addition to spi and qpi features, is25 lp 032/064 a lso support s dtr read. dtr allows high data throughput while running at lower clock frequencies. as dtr read option uses both rising and falling clock to drive output, the d ummy cycles are reduced by half as well . programmable drive strength and selectable b urst setting. the is25 l p 032/064 offers programmable output drive strength and selectable burst (wrap) length features to increase the efficiency and performance of read operations . the driver strength and burst setting f eatures are controlled by setting read registers. a t otal of s ix different drive strengths and four different burst size s ( 8/16/32/64bytes ) are selectable.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 4 rev. 0a 4/03/2014 table of contents 1. pin configuration ................................ ................................ ................................ ................................ ................. 6 2. pin descriptions ................................ ................................ ................................ ................................ .................... 7 3. block diagram ................................ ................................ ................................ ................................ ........................ 8 4. spi modes description ................................ ................................ ................................ ................................ ......... 9 5. system configuration ................................ ................................ ................................ ................................ ...... 11 5.1 block/sector addresses ................................ ................................ ................................ ........................... 11 6. registers ................................ ................................ ................................ ................................ ............................... 12 6.1. status register ................................ ................................ ................................ ................................ ............ 12 6.2. function register ................................ ................................ ................................ ................................ ....... 14 6.3 read registers ................................ ................................ ................................ ................................ .............. 15 7. protection mode ................................ ................................ ................................ ................................ ................. 17 7.1 hardware write protection ................................ ................................ ................................ .................... 17 7.2 software write protection ................................ ................................ ................................ ..................... 17 8. device operation ................................ ................................ ................................ ................................ ................. 18 8.1 normal read operation (nord, 03h) ................................ ................................ ................................ ........ 20 8.2 fast read data operation (f rd, 0bh) ................................ ................................ ................................ ...... 21 8.3 hold operation ................................ ................................ ................................ ................................ .............. 23 8.4 fast read dual i/o operation (frdio, bbh) ................................ ................................ ............................ 23 8.5 f a s t r e a d d u a l o u t p u t ope r a t i o n ( f rdo, 3bh) ................................ ................................ .................... 25 8.6 fast read quad i/o operation (frqio, ebh) ................................ ................................ ........................... 25 8.7 page program operation (pp, 02h) ................................ ................................ ................................ .......... 29 8.8 quad input page program operation (pp q , 32h/38h) ................................ ................................ .......... 31 8.9 erase operation ................................ ................................ ................................ ................................ ............ 32 8.10 sector erase operation (ser, d7h/20h) ................................ ................................ ................................ 33 8.11 block erase operation (ber32k:52h, ber64k:d8h) ................................ ................................ ............. 34 8.12 chip erase operation (cer, c7h/60h) ................................ ................................ ................................ ...... 36 8.13 write enable operation (wren, 06h) ................................ ................................ ................................ ..... 37 8.14 write disable operation (wrdi, 04h) ................................ ................................ ................................ ..... 38 8.15 read status register operation (rdsr, 05h) ................................ ................................ .................... 39 8.16 write status register operation (wrsr, 01h) ................................ ................................ .................. 40 8.17 read function register operation (rd f r, 48h) ................................ ................................ ................ 41 8.18 write function register operation (wr f r, 42h) ................................ ................................ .............. 42 8.19 enter quad peripheral interface (qpi) mode operation (qioen,35h; qiodi,f5h) ................... 43 8.20 program/erase suspend & resume ................................ ................................ ................................ ...... 44 8.21 deep power down (dp, b9h) ................................ ................................ ................................ ....................... 45 8.22 release deep power down (rdpd, abh) ................................ ................................ ................................ 46 8.23 set read parameters operation (srp, c0h) ................................ ................................ ....................... 46 8.24 read product identification (rdid, abh) ................................ ................................ ............................. 49 8.25 read product identification by jedec id operation (rdjdid, 9fh) ................................ ............ 51
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 5 rev. 0a 4/03/2014 8.26 read device manufacturer and device id operation (rdmdid, 90h) ................................ .......... 52 8.27 read unique id number (rduid, 4bh) ................................ ................................ ................................ ....... 54 8.28 read sfdp operation ( rdsfdp, 5ah) ................................ ................................ ................................ ....... 55 8.29 no operation (nop, 00h) ................................ ................................ ................................ .............................. 62 8.30 software reset (reset - enable (rsten , 66h ) and reset (rst , 99h ) ................................ .............. 62 8.31 mode reset operation (rstm, ffh) ................................ ................................ ................................ ........ 63 8.32 security information row ................................ ................................ ................................ ...................... 64 8.33 information row erase operation ( irer, 64h) ................................ ................................ .................. 64 8.34 information row program operation ( irp, 62h) ................................ ................................ ............... 65 8.35 information row read operation ( irrd, 68h) ................................ ................................ .................... 66 8.36 fast read dtr mode operation (f rdtr, 0dh) ................................ ................................ ...................... 67 8.37 fast read dual io dtr mode operation (f rddtr, bdh) ................................ ................................ .... 68 8.38 fast read quad io dtr mode operation (f rqdtr, edh) ................................ ................................ ... 69 8.39 sector lock/unlock functions ................................ ................................ ................................ ............. 70 9. electrical characteristics ................................ ................................ ................................ ........................... 72 9.1 absolute maximum ratings (1) ................................ ................................ ................................ .................... 72 9.2 operating range ................................ ................................ ................................ ................................ ........... 72 9.3 dc characteristics ................................ ................................ ................................ ................................ ...... 72 9.4 ac measurement conditions ................................ ................................ ................................ ..................... 73 9.5 ac characteristics ................................ ................................ ................................ ................................ ...... 74 9.6 serial input/output timing (1) ................................ ................................ ................................ .................... 75 9.7 power - up and power - down ................................ ................................ ................................ ....................... 76 9.8 program/erase performance ................................ ................................ ................................ .................. 76 10 . p ackage type information ................................ ................................ ................................ ......................... 78 10 .1 8 - pin jedec 208mil broad small outline integrated circuit (soic) package (jb) (1) ................................ ........ 77 10 .2 8 - contact ultra - thin smal l outline no - lead wson (6x5mm) (jk) (1) ................................ ................................ . 78 10 .3 8 - contact ultra - thin small outline no - lead wson (8x6 mm) (jl ) (1) ................................ ................................ . 79 10 .4 8 - pin 208mil vsop package (jf) (1) ................................ ................................ ................................ ................... 80 10 .4 16 - lead plastic small outline package (300 mils body width) (jm) (1) ................................ ................................ . 8 1
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 6 rev. 0a 4/03/2014 1. pin configuration ce# hold# (io3) si (io0 ) sck hold# (io3) vcc so (io1) wp# (io2) gnd 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 8 - pin soic 8 - pin wson 6x5mm 8 - pin wson 8x6mm 8 - pin soic 208mil 8 - pin vsop 208mil sck si( io0) 12 10 11 9 13 15 14 5 7 6 8 4 2 3 c e # v cc h old #(io3 ) nc nc nc nc so (io1) gnd si(io0) sclk nc nc nc nc wp#(io2) 16 - pin soic 300mil 1 6 1 so (io1) wp# (io 2 ) ce# gnd vcc
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 7 rev. 0a 4/03/2014 2. pin descriptions symbol type description ce# input chip enable: ce# low activates the internal circuitries for device operation. ce# high deselects the device and switches into standby mode to redu ce the power consumption. when the device is not selected, data will not be accepted via the serial input pin (sl), and the serial output pin (so) will remain in a high impedance state. sck input serial data clock si (io0) input /output serial data input /output so (io1) input/output serial data input/ output gnd ground vcc device power supply wp# (io 2 ) input /output write protect /serial data output : when the wp# pin is low, memory array write - protection depends on the setting of bp3, bp2, bp1 , and bp0 bits in the status register. h old# (io 3 ) input/output h old : pause serial communication by the master device without resetting the serial sequence. when the qe bit of status register is set for 1 , th e pin function becomes an i/o pin.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 8 rev. 0a 4/03/2014 3. block diagram wp# (io 2 ) control logic high voltage generator status register i/o buf f ers and data latches 256 bytes page buf f er y - decoder memory array x - decoder address latch & counter serial peripheral interf ace hold# (io3) so (io1) si (io0) wp# (io2) sck ce#
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 9 rev. 0a 4/03/2014 4. spi modes description multiple is25 lp 032/064 devices can be connected on the spi serial bus and controlled by a spi master, i.e. micro controller, as shown in figure 4 . 1 the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity . w hen the spi master is in s tand - by mode , the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 4 .2 and figure 4 .3. for both modes, the input data is latched on the rising ed ge of serial clock (sck), and the output data is available from the falling edge of sck. figure 4 . 1 connection diagram among spi master and spi slaves (memory devices) note : si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during qpi mode.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 10 rev. 0a 4/03/2014 figure 4 . 2 spi modes support figure 4 . 3 qpi modes support s c k s c k s o s i i n p u t m o d e m o d e 0 ( 0 , 0 ) m o d e 3 ( 1 , 1 ) m s b m s b 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 2 1 1 7 1 6 4 0 c e # s c k i o 0 2 0 1 3 5 1 i o 1 1 2 2 2 1 8 1 4 6 2 2 3 1 9 1 5 7 3 i o 2 i o 3 1 1 1 0 9 8 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 1 0 5 4 1 0 5 4 3 2 7 6 3 2 7 6 4 5 6 7 3 2 1 0 m o d e 3 m o d e 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 11 rev. 0a 4/03/2014 5. system configuration the is25 lp 032/064 is designed to interface directly with the synchronous serial peripheral interface (spi) of the motorola mc68hcxx series of microcontrollers or any spi interface - equipped system controllers. the memory array of is25 lp 032/064 is divided into uniform 4 kbyte sectors or uniform 32k/ 64 kbyte blocks (a block consists of sixteen adjacent sectors). table 5. 1 illustrates the memory map of the device. the status register controls how the memory is mapped. 5.1 block/sector address es table 5. 1 block/sector addresses of is25lp 032/064 memory density block no. (64kbyte) block no. (32kbyte) sector no. sector size (kbytes) address range 32mb 64mb block 0 block 0 sector 0 4 000000h - 0000ffh : : : block 1 : : : sector 15 4 00ff00h - 00ffffh block 1 block 2 sector 16 4 010000h C 0100ffh : : : block 3 : : : sector 31 4 01ff00h - 01ffffh block 2 block 4 sector 32 4 0 2 0000h - 0 2 00ffh : : : block 5 : : : sector 47 4 0 2 ff00h C 0 2 ffffh : : : : : block 63 block 126 : : : block 127 sector 1023 4 3 f ff00h C 3f ffffh : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : block 127 : : : : : : : block 255 : : : sector 2047 4 7fff00h C 7fffffh
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 12 rev. 0a 4/03/2014 6. registers the is25lp 032/064 has three sets of registers: status, function and read. 6.1. status register status register format and status register bit definitions are described in tables 6.1 & 6.2. table 6.1 status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip default (flash bit) 0 0 0 0 0 0 0 0 note : the default value of the bp3, bp2, bp1, bp0, and srwd bits were set to 0 at factory. table 6.2 status register bit definition bit name definition read - /write non - volatile bit bit 0 wip write in progress bit: "0" indicates the device is ready (default) "1" indicates a write cycle is in progress and the device is busy r no bit 1 wel write enable latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled r/w no bit 2 bp0 blo ck protection bit: (see tables 6.5 for details) "0" indicates the specific blocks are not write - protected (default) "1" indicates the specific blocks are write - protected r/w yes bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: 0 indicates the quad output function disable (default) 1 indicates the quad output function enable r/w yes bit 7 srwd status register write disable: (see table 7 .1 for details) "0" indicates the status register is not write - protected (default) "1" indicates the status register is write - protected r/w yes the bp0, bp1, bp2, bp3 , srwd , and qe are non - volatile memory cells that can be written by a write status register (wrsr) instruction. the default value of the bp2, bp1, bp0, and srwd bits were set to 0 at factory. the status register can be read by the read status register (rdsr). the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read - only, and can be used to detect the progress or complet ion of a program or erase operation. when the wip bit is 0, the device is ready for write status register, program or erase operation. when the wip bit is 1, the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the int ernal write enable latch. when the wel is 0, the write enable latch is disabled and all write operations, including write status register, write configuration register, page program, sector erase, block and chip erase operations are inhibited. when the w el bit is 1, write operations are allowed. the wel bit is set by a write enable (wren) instruction. each write register, program and erase instruction must be preceded by a wren instruction. the wel bit can be reset by a write disable (wrdi) instruction. it will automatically be the reset after the completion of any write operation .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 13 rev. 0a 4/03/2014 bp3, bp2, bp1, bp0 bits : the block protection ( bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to t ables 6. 3 for the block w rite protection (bp) bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected. any program or erase operation to that area will be inhibited. note : a chip erase (c er) instruction will be ignored unless all the block protection bits are 0s. srwd bit : the status register write disable (srwd) bit operates in conjunction with the write protection (wp#) signal to provide a hardware protection mode. when the srwd is s et to 0, the status register is not write - protected. when the srwd is set to 1 and the wp# is pulled low (v il ), the bits of status register (srwd, bp3, bp2, bp1, bp0) become read - only, and a wrsr instruction will be ignored. if the srwd is set to 1 a nd wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non - volatile bit in t he status register that allows q uad operation. when the qe bit is set to 0 , the pin wp# and hold# are enable d . when the qe bit is set to 1, the io2 and io3 pin s are enable d . warning: the qe bit must be set to 0 if wp# or hold# pin is tied directly to the power supply or ground. table 6 . 3 block assignment by block write protect (bp) bits. status register bits is25lp032 protected memory area (32mb) bp3 bp2 bp1 bp0 tbs (t/b selection) = 0, top area tbs (t/b selection) = 1, bottom area 0 0 0 0 0 ( none) 0 ( none) 0 0 0 1 1 (1 block : 63rd) 1 (1 block : 0th) 0 0 1 0 2 (2 block : 62nd and 63rd) 2 (2 block : 0th and 1st) 0 0 1 1 3 (4 blocks : 60th to 63nd) 3 (4 blocks : 0th to 3rd) 0 1 0 0 4 (8 blocks : 56th to 63rd) 4 (8 blocks : 0th to 7th) 0 1 0 1 5 (16 blocks :48th to 63rd) 5 (16 blocks : 0th to 15th) 0 1 1 0 6 (32 blocks : 32nd to 63rd) 6 (32 blocks : 0th to 31st) 0 1 1 1 7 (64 blocks : 0th to 63rd) 7 (64 blocks : 0th to 63rd) 1 x x x 8 (128 blocks : 127th to 255th) all blocks 8 (128 blocks : 0th to 127th) all blocks *note x is dont care status register bits IS25LP064 protected memory area (64mb) bp3 bp2 bp1 bp0 tbs (t/b selection) = 0, top area tbs (t/b selection) = 1, bottom area 0 0 0 0 0 ( none) 0 ( none) 0 0 0 1 1 ( 1 block : 127 th) 1 ( 1 block : 0th) 0 0 1 0 2 ( 2 block : 126th and 127 th) 2 ( 2 block : 0th and 1st) 0 0 1 1 3 ( 4 blocks : 124th to 127 th) 3 ( 4 blocks : 0th to 3rd) 0 1 0 0 4 ( 8 blocks : 120th to 127 th) 4 ( 8 blocks : 0th to 7th) 0 1 0 1 5 ( 16 blocks : 112 nd to 127 th) 5 ( 16 blocks : 0th to 15th) 0 1 1 0 6 ( 32 blocks : 96th to 127 th) 6 ( 32 blocks : 0th to 31st) 0 1 1 1 7 ( 64 blocks : 64th to 127th ) 7 ( 64 blocks : 0th to 63rd) 1 x x x 8 (128 blocks : 0 th to 127th ) 8 (128 blocks : 0th to 127th) *note x is dont care
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 14 rev. 0a 4/03/2014 6.2. f unction register function registe r format and bit definition are described in table 6.4 and 6.5 table 6 . 4 function register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irl3 irl2 irl1 irl0 esus psus tb s reserved default 0 0 0 0 0 0 0 1 note: bit 0 reserved and must be set to 1 table 6. 5 function register bit definition bit name definition read /write non - volatile bit bit 0 reserved reserved set to 1 reserved reserved bit 1 top/bottom sel ect ion top/bottom selection . ( see tables 6.5 for details ) 0 indicates top area. 1 indicates bottom area. r/w yes bit 2 psus program suspend bit: 0 indicates program is not suspend 1 indicates program is suspend r no bit 3 esus erase suspend bit : "0" indicates erase is not suspend "1" indicates erase is suspend r no bit 4 ir lock 0 lock the information row 0: 0 indicates the information row can be program med 1 indicates the information row can not be program med r/w yes bit 5 ir lock 1 lock the information row 1: 0 indicates the information row can be program med 1 indicates the information row can not be program med r/w yes bit 6 ir lock 2 lock the information row 2: 0 indicates the information row can be program med 1 indicates the information row can not be program med r/w yes bit 7 ir lock 3 lock the information row 3: 0 indicates the information row can be program med 1 indicates the information row can not be program med r/w yes note: table 6.5 function register bits 4 - 7 are one time programmable and cannot be modified top/bottom selection : bp0~3 area assignment changed from top or bottom. see tables 6.5 for details psus bit : the program suspend status bit indicates when a program operation has been suspended. the psus changes to 1 after a suspend command is issued during the p rogram operation. once the suspended program resumes, the psus bit is reset to 0. esus bit : the erase suspend status indicates when an erase operation has been suspended. the esus bit is 1 after a suspend command is issued during an erase operation. once the suspended erase resumes, the esus bit is reset to 0. ir lock bit 0 ~ 3 : the information row lock bit s are programmable . if the bit set to 1, it can t be programmed.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 15 rev. 0a 4/03/2014 6.3 read registers read register format and bit definitions pertaining to qpi mode are described below. read parameter bits table 6.6 defines all bits that control features in spi/qpi modes. the ods2, ods1, ods0 (p7,p6,p5) bits provide a method to set and control driver strength. the dummy cycle bits (p4, p3) define how m any dummy cycles are used during various read modes. the wrap length bits (p2, p1, p0) define whether or not wrap around is enabled and the depth of data to wraparound on. the set read parameters operation (srp, c0h) is used to set all the read register bits, and can thereby define the output driver strength, number of dummy cycles used during read modes, burst length and the data wrapping features. table 6 .6 read parameter table p7 p6 p5 p4 p3 p2 p1 p0 ods2 ods1 ods0 dummy cycles dummy cycles wrap enable wrap length wrap length default (flash bit) 1 1 1 0 0 0 0 0 table 6 .7 burst length data p1 p0 8 bytes 0 0 16 bytes 0 1 32 bytes 1 0 64 bytes 1 1 table 6 .8 wrap function p2 disable 0 enable 1
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 16 rev. 0a 4/03/2014 table 6.9 r e ad dummy cycles. read modes p4,p3 = 00 p4,p3 = 01 p4,p3 = 10 max freq mode normal read 03h 0 0 0 50mhz spi fast read 0bh 8 8 8 133mhz spi fast read 0bh 6 4 8 4cc : 84mhz 6cc : 10 4 mhz 8cc : 133mhz qpi dual io read 1 bbh 4 4 8 4cc : 104mhz 8cc : 133mhz spi fast read dual output 3bh 8 8 8 133mhz spi quad io read 2 ebh 6 4 8 4cc : 84mhz 6cc : 10 4 mhz 8cc : 133mhz spi , qpi note s : 1. when 4 dummy cycles are used the max clock frequency is 104mhz; when 8 dummy cycles are used the max clock frequency is 133mhz . 2. when 4 dummy cycles are used the max clock frequency is 84mhz; when 6 dummy cycles are used the max clock frequency is 10 4 mhz ; when 8 dummy cycles are used the max clock frequency is 133mhz . 3. i n dtr mode the dummy cycles are reduced by half . table 6 . 10 driver strength table ods2 ods1 ods0 description remark 0 0 0 reserved 0 0 1 12.50% 0 1 0 25% 0 1 1 37.50% 1 0 0 reserved 1 0 1 75% 1 1 0 100% 1 1 1 50% default
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 17 rev. 0a 4/03/2014 7. protection mode the is25 lp 032/064 supports hardware and software write - protection mecha nisms . 7.1 hardware write protection the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp 1 , bp0 , srwd , and qe in the status register. refer to the section 6.1 status register. w rite inhibit voltage is 2.1 v. a ll write sequence will be ignored when vcc drop s to 2.1 v or lower. 7.2 software write prote ction the is25 lp 032/064 also provide a sof tware write protection feature . the block protection ( bp3, bp2, bp1, bp0) bits allow part or the whole memory area to be write - protected. table 7 .1 hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable note : before the execution of any program, erase or write status register instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled, the program, erase or write register instruction will be ignored.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 18 rev. 0a 4/03/2014 8. device operation the is25 lp 032/064 utilizes an 8 - bit instruction register. refer to table 8 .1. instruction set for details on instructions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (ms b ) first on serial data input (si). the input data on si is latched on the rising edge of serial clock (sck) after chip enable (ce#) is driven low (v il ). every instruction sequence starts with a one - byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in to end the operation. table 8 . 1 instruction set instruction name operation total bytes mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 comments nord normal read mode 4 spi 03h a <23:16> a <15:8> a <7:0> data out frd fas t read mode 5 spi qpi 0bh a <23:16> a <15:8> a <7:0> dummy byte data out frdio fast read dual i/o 3 spi bbh a <23:16> dual a <15:8> dual a <7:0> dual axh dual dual data out frdo fa st read dual output 5 spi 3bh a <23:16> a <15:8> a <7:0> dummy byte dual data out frqio fast read quad i/o 2 spi qpi ebh a <23:16> quad a <15:8> quad a <7:0> quad axh quad quad data out frdtr f ast read dtr mode 5 spi qpi 0dh a <23:16> a <15:8> a <7:0> dummy byte dual data out frddtr fast read dual i/o dtr 3 spi bdh a <23:16> dual a <15:8> dual a <7:0> dual axh dual dual data out frqdtr fast read quad i/o dtr 5 spi qpi edh a <23:16> a <15:8> a <7:0> dummy byte quad data out pp input page program 4 + 256 spi qpi 02h 02h a <23:16> a <15:8> a <7:0> pd +256byte ppq qua d input page program 4 + 256 spi 32h 38h a <23:16> a <15:8> a <7:0> pd +256byte quad ser sector erase 4 spi qpi d7h 20h a <23:16> a <15:8> a <7:0> ber32 ( 32kb) block erase 32k 4 spi qpi 52h a <23:16> a <15:8> a <7:0> ber64 (64kb) block erase 64k 4 spi qpi d8h a <23:16> a <15:8> a <7:0> cer chi p erase 1 spi qpi c7h 60h wren write enable 1 spi qpi 06h wrdi wr ite disable 1 spi qpi 04h rdsr read status register 2 spi qpi 05h sr wrsr wr ite status register 2 spi qpi 01h wsr data rdfr read function register 2 spi qpi 48h data out
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 19 rev. 0a 4/03/2014 instruc tion name operation total bytes mode byte0 byte1 byte2 byte3 byte4 byte5 byte6 comments wrfr write function register 2 spi qpi 42h wfr data qioen enter quad io mode (qpi) 1 spi 35h qiodi e xit quad io mode(qpi) 1 qpi f5h persus suspend during program/erase 1 spi qpi 75h b0h perrsm resume program/erase 1 spi qpi 7ah 30h power down power down 1 spi qpi b9h rdid, r dpd read id / release power down 4 spi qpi abh dummy byte dummy byte dummy byte id7 - id0 srp set read parameters 4 spi qpi c0h data in rdjdid read jedec id command 1 9fh mid id15 - 8 id7 - id0 rdmdid read manufacturer & device id 4 spi qpi 90h xxh xxh 00h mid id7 - id0 01h did mid1 rdidq read id qpi mode 4 qpi afh mid id15 - 8 id7 - id0 rduid read unique id 4 spi qpi 4bh xxh xxh 0xh data out rdsf dp sfdp read 5 spi qpi 5ah a <23:16> a <15:8> a <7:0> dummy byte data out rsten software reset enable 1 spi qpi 66h rst sof tware reset 1 spi qpi 99h rstm mode reset 1 spi qpi ffh irer er ase information row 4 spi qpi 64h a <23:16> a <15:8> a <7:0> irp program information row 4 + 256 spi qpi 62h a <23:16> a <15:8> a <7:0> pd +256byte irrd read information row 4 spi qpi 68h a <23:16> a <15:8> a <7:0> data out
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 20 rev. 0a 4/03/2014 8.1 normal read operation ( no rd, 03 h ) the normal read data ( no rd) instruction is used to read memory contents of the is25 lp 032/064 at a maximum frequency of 50 mhz . the no rd instruction code is transmitted via the sl line, followed by three address bytes (a23 - a0) of the first memory location to be read. a total of 24 address bits are shifted in, but only a ms b (most significant bit ) - a 0 are deco ded. the remaining bits (a23 C a ms b ) are ignored. the first byte address can be at any memory location. upon completion, any data on the sl wi ll be ignored. refer to table 8 . 2 for the related address key. the fir st byte data (d7 - d0) address is shifted out on the so line, ms b first. a single byte of data, or up to the whole memory array, can be read out in one read instruction. the address is automatically incremented after each byte of data is shifted out. the r ead operation can be terminated at any time by driving ce# high (vih) after the data comes out. when the highest address of the device is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one conti nuous read instruction. if a read data instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle . table 8 .2 address key address is25 lp 032/064 a n ( a ms b C a 0) a 23 - a0 figure 8 . 1 read data sequence 0 i n s t r u c t i o n = 0 0 0 0 0 0 1 1 b 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 7 6 5 3 2 4 1 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 21 rev. 0a 4/03/2014 8.2 fast read data opera tion ( f r d , 0b h ) the fast read (frd) instruction is used to read memory data at up to a 1 33 mhz clock. the fast read instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte from the address is shifted out on the so line, w ith each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast read instruction. the fast read instruction is terminated by driving ce# high (vih). if a fast read data instruction is issued whil e an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycl e . figure 8 .2 fast read data sequence d u m m y b y t e 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t 4 2 4 3 4 4 4 5 4 6 4 7 h i g h i m p e d a n c e 0 i n s t r u c t i o n = 0 b h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 . . . . . .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 22 rev. 0a 4/03/2014 fast read data qpi operation ( fr d qpi, 0 bh) the qpi fast read (frd qpi) instruction is used to read memory data at up to a 1 33 mhz clock. the fast read instruction code (2 clocks) is follo wed by three address bytes (a23 - a0 6clocks ) and mode bits, dummy byte ( 4 clocks), transmitted via the qpi line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. . the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast_read instruction. the fast_read instruction is terminated by driving ce# high (vih). if a fast read data instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is i gnored and will not have any effects on the current cycle figure 8 . 3 fast read data sequence , qpi mode note : number of dummy cycles depends on read parameter setting . detailed information in table 6.9 read dummy cycles . 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 c e # s c k i o [ 3 : 0 ] 0 b h a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s 6 d u m m y c y c l e d a t a 1 d a t a 2 7 : 4 3 : 0 7 : 4 3 : 0 1 6 1 7
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 23 rev. 0a 4/03/2014 8.3 hold operation hold# is used in conjunction with ce# to select the is25 lp 032/064 . when the device is selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still toggle duri ng hold). inputs to sl o will be ignored while so is in the high impedance state. note : hold is not supported in dtr mode or with qe=1. timing graph can be referenced in ac parameters figure 9.3 8.4 fast read dual i/o operation ( frdio, bb h ) the frdio allows the address bits to be input two bits at a time. this may allow for code to be executed directly from the spi in some applications. the frdio instruction code is followed by three address bytes (a23 C a0) and a mode byte, transmitted via the io0 and io1 lines, with each pair of bits latched - in during the rising edge of sck. the address msb is input on io1, the next bit on io0, and continues to shift in alternating on the two lines. the mode b it contains the value ax, where x is a dont ca re value. then the first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bits shifted out at a maximum frequency f ct , during the falling edge of sck. the msb is output on io1, while simultaneously the second bit is output on io0. figure 8 . 4 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdio instruction. frdio instruction is terminated by driving ce# high (v ih ). the device expects the next operation will be another frdio. it remains in this mod e until it receives a mode reset (ffh) command. in subsequent frdio execution, the command code is skipped. it saves timing cycles as described in figure 8 . 5 . if a frdio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 24 rev. 0a 4/03/2014 figure 8 . 4 fast read dual i/o sequence (with command decode cycles) note : number of dummy cycles depends on read parameter setting . detailed information in table 6.9 read dummy cycles . figure 8 . 5 fast read dual i/o sequence (without command decode cycles) notes : if the mode bits=ax (x dont care), it can execute the continuous read mode (without command) . number of dummy cycles depends on read parameter setting . detail ed information in table 6.9 read dummy cycles . 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 8 1 9 2 0 2 1 . . . i n s t r u c t i o n = 1 0 1 1 1 0 1 1 b . . . 2 1 3 - b y t e a d d r e s s c e # s c k i o 0 c e # s c k i o 0 i o 1 . . . 2 2 i o 1 1 9 m o d e b i t s 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 d a t a o u t 1 d a t a o u t 2 7 6 i o s w i t c h f r o m i n p u t t o o u t p u t 2 2 2 3 2 0 0 2 6 4 1 3 7 5 0 1 2 3 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 d u m m y c l o c k s 2 1 d a t a o u t 1 d a t a o u t 2 2 3 2 4 . . . 2 1 3 C b y t e a d d r e s s . . . 2 2 1 9 m o d e b i t s 2 2 2 3 2 0 0 2 6 4 1 3 7 5 4 6 2 6 4 0 2 0 5 7 3 7 5 1 3 1
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 25 rev. 0a 4/03/2014 8.5 f a s t r e a d d u a l o u t p u t ope r a t i o n ( f rdo, 3bh) t he f rdo i n s t r u c t i o n i s u s ed to r ead m e m o r y da t a o n two o utp u t p i ns ea c h at up t o a 1 33 mhz c l o c k . t he f rdo i n s t r u c t i o n c o d e i s f o ll o wed b y th r e e add r e s s b y tes ( a 23 C a 0) a nd a du m m y b y te ( 8 c l o c k s ) , t r an s m i tted v i a t h e s i l i n e, w i th ea c h b i t l at c h e d - i n du ri ng t he r i s i ng edge of s c k . t hen t h e f i rs t data b y t e a dd r e ss ed is s h i ft ed o ut o n t h e s o and s io li n e s , w i th e a c h p a i r of b i ts s h i f ted o u t at a m a x i m u m f r equen c y f c t , du ri ng t he f a l li n g e dge of s c k . t he f i rs t b i t ( msb ) i s ou t put on s o , wh i l e s i m u l ta n eou s l y the s e c ond b i t i s ou t put on s i o . t he f i rs t b y t e a dd r e ss ed c a n be at an y m e m o r y l o c a t i on. t he add r e s s i s au t o m at i c a l l y i n cr e m ented a f ter ea c h b y te of data i s s h i f ted o ut. w hen the h i g he s t add r e s s i s r ea c h ed, the a d d r e s s c ounter w i l l r o l l o v er t o the 0 00 0 00h a d d r e ss , a l l o w i ng the en t i r e m e m o r y t o be r ead w i th a s i n g l e f rdo i n s t r u c t i on. f r do i n s t r u c t i on i s te r m i nated b y d ri v i ng c e # h i gh ( vih ) . if a f rdo i n s t r u c t i on i s i ss ued wh i l e an e r a s e, p r og r am o r w r i te c y cl e i s i n p r o c e s s ( b u s y =1) the i n s t r u c t i on i s i gno r ed and w il l not ha v e any ef f e c ts on the c u rr ent c y cl e. f i gu re 8 . 6 f ast read d u a l - outpu t s e qu e n ce 8.6 fast read quad i/o operation ( frqio, ebh) 7 5 c e # s c k s i 3 s o 1 d a t a o u t 1 4 2 4 3 4 4 4 5 4 6 4 7 h i g h i m p e d a n c e 0 i n s t r u c t i o n = 3 b h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 . . . . . . 6 4 2 0 h i g h i m p e d a n c e . . . d a t a o u t 2 7 5 3 1 6 4 2 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 26 rev. 0a 4/03/2014 the frqio instruction allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 C a0) and a mode byte, transmitted via the io3, io2, io 0 and io1 lines, with each group of four bits latched - in during the rising edge of sck. the address of msb input s on io3, the next bit on io2, the next bit on io1, the next bit on io0, and continue to shift in alternating on the four. the mode byte contain s the value ax, where x is a dont care value. after four dummy clocks, t he first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with each group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit ( msb ) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 8 . 7 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio instruction. frqio instruction is te rminated by driving ce# high (v ih ). the device expects the next operation will be another frqio. it remains in this mode until it receives a mode reset (ffh ) command. in subsequent frdio execution, the command code is not input, saving cycles as described in figure 8 . 8 . if a frqio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have an y effects on the current cycle .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 27 rev. 0a 4/03/2014 figure 8 . 7 fast read quad i/o sequence (with command decode cycles) note : number of dummy cycles depends on clock speed. detailed information in table 6.9 read dummy cycles 0 i n s t r u c t i o n = e b h 2 0 c e # s c k 4 i o 1 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 2 8 0 4 m o d e b i t s 2 1 5 1 7 1 3 9 1 5 i o 2 2 2 6 1 8 1 4 1 0 2 6 i o 3 2 3 7 1 9 1 5 1 1 3 7 i o 0 s c k 2 6 2 7 . . . . . . 2 2 2 3 2 4 2 5 2 0 2 1 1 6 1 7 1 8 1 9 i o 0 i o 1 i o 2 i o 3 4 4 0 4 0 0 4 5 5 1 5 1 1 6 6 6 2 6 2 2 6 7 7 3 7 3 3 7 0 1 2 3 4 5 6 7 4 d u m m y c y c l e s d a t a o u t 1 d a t a o u t 2 d a t a o u t 3 d a t a o u t 4 c e #
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 28 rev. 0a 4/03/2014 figure 8 . 8 fast read quad i/o sequence (without command decode cycles) note : number of dummy cycles depends on clock speed. detailed information in table 6.9 read dummy cycles 0 c e # s c k i o 1 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 4 m o d e b i t s 5 i o 2 6 i o 3 7 i o 0 2 0 4 1 6 1 2 8 0 4 2 1 5 1 7 1 3 9 1 5 2 2 6 1 8 1 4 1 0 2 6 2 3 7 1 9 1 5 1 1 3 7 0 1 2 3 4 d u m m y c l o c k s d a t a o u t 1 d a t a o u t 2 4 5 6 7
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 29 rev. 0a 4/03/2014 8.7 pa ge program operation ( pp, 02 h ) the page program ( pp ) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp2, bp1, bp0) bits. a p p instruction which attempts to program into a page that is write - protected will be ignored. before the execution of pp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the pp instruction code, three ad dress bytes and program data (1 to 256 bytes) are input via the sl line. program operation will start immediately after the ce# is brought high, otherwise the pp instruction will not be executed. the internal control logic automatically handles the program ming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if t he wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note : a program operation can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without firs t erasing the whole sector or block.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 30 rev. 0a 4/03/2014 figure 8 . 0 9 page program sequence figure 8 . 1 0 page program sequence (qpi) 02h 0 i n s t r u c t i o n = 0 b h 2 3 c e # s c k s i 3 s o 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 2 0 7 5 7 6 5 2 1 0 2 0 7 6 2 0 7 7 2 0 7 8 2 0 7 9 4 3 2 1 0 1 s t b y t e d a t a - i n 2 5 6 t h b y t e d a t a - i n 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 c e # s c k i o [ 3 : 0 ] 0 2 h a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s 7 : 4 3 : 0 7 : 4 3 : 0 7 : 4 3 : 0 7 : 4 3 : 0 d a t a 1 d a t a 2 . . . d a t a 2 5 6
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 31 rev. 0a 4/03/2014 8.8 quad input page program operation ( pp q , 32h/ 38h) the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3) . the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to program into a page that is write - protected will be ignored. before the execution of quad input page program instruction, the qe bit in the status register must be set to 1 and the write enable latch (wel) must be enabled through a write enable (wren) instruction. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3). program operation will start immediately after the ce# is brought high, otherwise the quad input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instructi on. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched da ta are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to b e programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note : a program operation can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 8 .1 1 quad input page program operation 0 i n s t r u c t i o n = 3 2 h / 3 8 h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 2 2 2 1 . . . 3 2 3 3 3 4 3 5 5 1 5 1 s o 6 2 6 2 s o 7 3 7 3 4 0 4 0 d a t a i n 1 d a t a i n 2
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 32 rev. 0a 4/03/2014 8.9 erase operation the memory array of the is25 lp 032/064 is organized into uniform 4 kbyte sectors or 32k/ 64 kbyte uniform blocks (a block consists of sixteen adjacent sectors). before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to 1). in order to eras e the device, there are three erase instructions available: sector erase ( ser ), block erase ( ber) and chip erase (c er). a sector erase operation allows any individual sector to be erased without affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory array of a device. a sector erase, block erase or chip erase operation can be executed prior to any programming operation.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 33 rev. 0a 4/03/2014 8.10 sector erase operati on (ser, d7h/20h ) a sector erase (ser) instruction erases a 4 kbyte sector before the execution of a ser instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is reset automatically after the completion of sector an erase o peration. a se r instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the se r instruction code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase voltage and timing. refer to figure 8. 1 2 - 8.1 3 for the sector erase sequence. during an erase operation, all instruction will be ignored except the read status register (rdsr) instr uction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instruction. if the wip bit is 1, the erase operation is still in progress. if the wip bit is 0, the erase operation has been completed. figure 8 . 1 2 sector erase sequence figure 8 . 1 3 sector erase sequence (qpi) 0 i n s t r u c t i o n = d 7 h / 2 0 h 2 3 c e # s c k s i 3 s o 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 2 1 0 0 1 2 3 4 5 6 7 c e # s c k i o [ 3 : 0 ] d 7 h / 2 0 h a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 34 rev. 0a 4/03/2014 8.11 block erase operatio n (ber32k: 52h , ber64k: d8h ) a block erase (ber) instruction erases a 32/ 64 kbyte block of the is25 lp 032/064 . before the execution of a ber instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase operation. the ber instruction cod e and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the ber instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. refer to fig ure 8.1 4 - 8.1 7 for the block erase sequence. figure 8 . 1 4 block erase (64k) sequence figure 8 . 1 5 block erase (64k) sequence (qpi) 0 1 2 3 4 5 6 7 c e # s c k i n s t r u c t i o n = 5 2 h 2 2 a d d r e s s 8 9 2 9 3 0 3 1 2 3 a 2 a 1 a 0 s i 0 1 2 3 4 5 6 7 c e # s c k i o [ 3 : 0 ] d 8 h a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 35 rev. 0a 4/03/2014 figure 8 . 1 6 block erase sequence (32k) figure 8 . 1 7 block erase (32k) sequence (qpi) 0 1 2 3 4 5 6 7 c e # s c k i n s t r u c t i o n = d 8 h 2 2 a d d r e s s 8 9 2 9 3 0 3 1 2 3 a 2 a 1 a 0 s i 0 1 2 3 4 5 6 7 c e # s c k i o [ 3 : 0 ] 5 2 h a 5 a 4 a 3 a 2 a 1 a 0 a d d r e s s
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 36 rev. 0a 4/03/2014 8.12 chip erase operation (cer, c7h/60h ) a chip erase (c er ) instruction erases the entire memory array of a is25 lp 032/064 . before the execution of c er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after completion of a chip erase operation. the c er instruction code is input via the si. erase operation will start immediately a fter ce# is pulled high, otherwise the cer instruction will not be executed. the internal control logic automatically handles the erase voltage and timing. refer to figure 8. 1 8 - 8. 19 for the chip erase sequence. figure 8 . 1 8 chip erase sequence figure 8 . 19 chip erase sequence (qpi) i n s t r u c t i o n = 6 0 h / c 7 h c e # s c k s i o s o h i g h i m p e d a n c e 6 7 4 5 2 3 0 1 0 1 c e # s c k i o [ 3 : 0 ] 6 0 h / c 7 h
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 37 rev. 0a 4/03/2014 8.13 write enable operati on ( wren, 06 h ) the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit of the is25 lp 032/064 is reset to the write C protected state after power - up. the wel bit must be write enabled before any write operation, including sector, block erase, chip erase, page program, write status register, and write configuration register operations. the wel bit will be reset to the write - protect state automatically upon completion of a write operation. the wren instruction is required before any above operation is executed. figure 8 . 2 0 write enable sequence figure 8 . 2 1 write enable operation (qpi) i n s t r u c t i o n = 0 0 0 0 0 1 1 0 b c e # s c k s i o s o h i g h i m p e d a n c e 6 7 4 5 2 3 0 1 0 1 c e # s c k i o 0 i o 1 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 38 rev. 0a 4/03/2014 8.14 write disable operat ion ( wrdi, 04 h ) the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is autom atically reset. figure 8 . 2 2 write disable sequence figure 8 . 2 3 write dis able operation (qpi) i n s t r u c t i o n = 0 0 0 0 0 1 0 0 b c e # s c k s i o s o h i g h i m p e d a n c e 6 7 4 5 2 3 0 1 0 1 c e # s c k i o 0 i o 1 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 39 rev. 0a 4/03/2014 8.15 read status register operation ( rdsr, 05 h ) the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write status register operation, all other instructions will be ignored except the rdsr instruction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8 . 2 4 read status register sequence figure 8 . 2 5 6 rdsr command (read status register) operation (qpi) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 i n s t r u c t i o n = 0 5 h 7 6 c e # s c k s i 5 3 2 s o 4 1 4 1 5 1 0 d a t a o u t 0 1 2 3 c e # s c k i o [ 3 : 0 ] 0 5 h 7 : 4 3 : 0 d a t a c o m m a n d
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 40 rev. 0a 4/03/2014 8.16 write status registe r operation ( wrsr, 01 h ) the write status register (wrsr) instruction allows the user to enable or disable the block protection and status register write protection features by writing 0s or 1s into the non - volatile bp3, bp2, bp1, bp0 , qe and srwd bits. figure 8 . 2 6 write status register sequence figure 8 . 2 7 wrsr command (write status register) operation (qpi) data in 0 1 2 3 d 5 d 1 d 0 c e # s c k i o 0 d 4 i o 1 d 6 d 2 d 7 d 3 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 41 rev. 0a 4/03/2014 8.17 read function register operation ( rd f r, 48 h ) the read function register (rd f r) instruction provides access to the erase/program suspend register . during the execution of a program, erase or write status register suspend , which can be used to check the suspend status . figure 8 . 2 8 read function register sequence figure 8 . 29 read function register operation (qpi) rd f r 0 i n s t r u c t i o n = 4 8 h 7 c e # s c k s i 3 s o d a t a o u t 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 h i g h i m p e d a n c e 6 5 4 2 1 0 m s b 0 1 2 3 d 5 d 1 d 0 c e # s c k i o 0 d 4 i o 1 d 6 d 2 d 7 d 3 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 42 rev. 0a 4/03/2014 8.18 write function register operation ( wr f r, 42h) the write function register (wr f r) instruction allows the user to lock the information row by bit 0. (ir lock) figure 8 . 3 0 write function register sequence figure 8 . 3 1 wr f r command (write function register) operation (qpi) data in 0 1 2 3 d 5 d 1 d 0 c e # s c k i o 0 d 4 i o 1 d 6 d 2 d 7 d 3 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 43 rev. 0a 4/03/2014 8.19 enter quad peripheral interface (qpi) mode operation (qioen,35h; qiodi,f5h) the enter quad i/o (enqio) instruction, 35h, enables the flash device for qpi bus operation. upon completion of the instruction, all instructions thereafter will be 4 - bit multiplexed input/output until a power cycle or a exit quad i/o instruction instruc tion. figure 8. 3 2 enter quad peripheral interface operation (qpi) figure 8. 3 3 exit quad peripheral interface (qpi) mode operation the exit quad i/o instruction, f5 h , resets the device to 1 - bit spi protocol operation. to execute a exit quad i/o operation, the host drives ce# low, sends the exit quad i/o command cycle then, drives ce# high. the device just accepts sqi (2 clocks) command cycles. i n s t r u c t i o n = 0 0 1 1 0 1 0 1 b c e # s c k s i o s o h i g h i m p e d a n c e 6 7 4 5 2 3 0 1 0 1 c e # s c k i o 0 i o 1 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n = f 5 h
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 44 rev. 0a 4/03/2014 8.20 program/erase suspen d & resume the device allows the interruption of sector - erase, block - erase or page - program operations to conduct other operations. b0h command for suspend and 30h for resume will be used. (spi/qpi all acceptable) function register bit2 (psus) and bit3 (esus) are used to check whether or not the device is in suspend mode. suspend to read ready timing: 10 0s. resume to another suspend timing: 40 0s (recommendation) . program/erase suspen d during sector - erase or block - erase (persus 75h/ b0h) after erase suspend, wel bit will be disabled, therefore only read related, resume and reset commands will be accepted (03h, 0bh, bbh, ebh, 05h, abh, 30h, 9fh, abh, 90h, 4bh, 00h, 66h, 99h, afh, c0h). to execute a program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (b0h), then drives ce# high. the function register indicates that the erase has been suspended by changing the esus bit from 0 to 1, but the device will not acce pt another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait t su s . when esus bit is issued, the write enable latch (wel) bit will be reset. program/erase suspen d during page programming (persus 75h/ b0h) program suspend allows the interruption of all program operations. after a program suspend command, wel bit will be disabled, only read related, resume and reset command can be accepted (03h, 0bh, bbh, ebh, 05h, abh, 30h, 9fh, abh, 90h, 4bh, 00h, 66h, 99h, afh, c0h). to execute a program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle (b0h), then drives ce# high. the function register indicates that the programming has been suspend ed by changing the psus bit from 0 to 1, but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status register or wait t su s . program/erase resume (perrsm 7a/ 30 h) program/erase resume restarts a program/erase command that was suspended, and changes the suspend status bit in the (esus or psus bits) back to 0. to execute a program/erase resume operation, the host drives ce# low, sends the program/erase resume com mand cycle (30h), then drives ce# high. a cycle is two nibbles long, most significant nibble first. to determine if the internal, self - timed write operation completed, poll the wip bit in the status register, or wait the specified time t se , t be or t pp for sector - erase, block - erase, or page - programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 45 rev. 0a 4/03/2014 8.21 deep power down ( dp, b9h) the deep power - down (dp) instruction is for setting the device on the minimizing the power consumption (enter into power - down mode), the standby current is reduced from i sb1 to i sb2 ). during the power - down mode, the device is not active and all write/program/ erase instructions are ignored. the instruction is initiated by driving the ce# pin low and shifting the instruction code b9h as show in the figure 8.34 . the ce# pin must be driven high after the instruction has been latched. if this is not done the powe r - down will not be executed. after ce# pin driven high, the power - down state will entered within the time duration of t dp . while in the power - down state only the release from power - down / rdid instruction, which restores the device to normal operation, wil l be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. it can support in spi and qpi mode. figure 8. 3 4 enter deep power down mode operation. (spi) figure 8. 3 5 deep power down sequence (qpi) 0 1 2 3 4 5 6 7 . . . i n s t r u c t i o n = 1 0 1 1 1 0 0 1 b . . . c e # s c k s i t d p 0 1 c e # s c k i o 0 i o 1 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n t d p
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 46 rev. 0a 4/03/2014 8.22 release deep power d own (rdpd, abh ) the release from power - down /read device id instruction is a multi - purpose instruction. to release the device from the power - down state mode, the instruction is issued by driving the ce# pin low, shifting the instruction code abh and driving ce# high as show n in figure 8.36, 8.37 release from power - down will take the time duration of t res1 before the device will resume normal operation and other instructions are accepted. the ce# pin must remain high during the t res1 time duration. if the release from power - d own / rdid instruction is issued while an erase, program or write cycle is in process (when wip equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 8. 3 6 release power down sequence (spi) figure 8. 3 7 release power down sequence (qpi) 8.23 set read parameters operation (srp, c0h ) 0 1 2 3 4 5 6 7 . . . i n s t r u c t i o n = 1 0 1 0 1 0 1 1 b . . . c e # s c k s i t r e s 1 0 1 c e # s c k i o 0 i o 1 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 t r e s 1 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 47 rev. 0a 4/03/2014 set read operational driver strength this device supports configurable operational driver strengths in both spi and qpi mode by setting three bits within the read register (ods0, ods1, ods3). to set the ods bits the srp operation (c0h) instruction is required. the devices driver strength can be reduced as low as 12.50% of full drive strength. details r egarding the driver streng t h can be found in table 6.10. note: the default driver strength is set to 50% figure 8. 38 set read parameters operation. figure 8. 39 set read parameters operation. (qpi) 0 i n s t r u c t i o n = c 0 h 7 c e # s c k s i 3 s o d a t a i n 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 h i g h i m p e d a n c e 6 5 4 2 1 0 0 1 2 3 d 5 d 1 d 0 c e # s c k i o 0 d 4 i o 1 d 6 d 2 d 7 d 3 i o 2 i o 3 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 i n s t r u c t i o n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 48 rev. 0a 4/03/2014 read with 8/16/32/64 - byte wrap around this device supports burst read in both spi and qpi mode and defines the wrap around feature enable . to set the burst length, following command operations are required: c0h in the first byte (8 - clocks), 0h to enable wrap around and to define the data to wrap around on and 1h to disable wrap around. the wrap around unit is defined within the one page, 256byte s , with random initial address. wrap around mode disabled for the default state of the device. to e xit wrap around, it is required to issue another c0 command to set bit3 = 0. otherwise, wrap around status will be retained until power down or reset operations. to change wrap around depth, it is required to issue another c0 command to set bit0 and bi t1 ( detailed information in table 6.7 burst length data ). qpi 0bh ebh and spi (ebh, 03h, 0bh, bbh) support wrap around feature after wrap around enable. refer to figures 8.38 and 8.39 for instruction sequence.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 49 rev. 0a 4/03/2014 8.24 read product identification (rdid, abh ) the release from power - down /read device id instruction is a multi - purpose instruction. it can support bot h spi and qpi mode. the read product identification (rdid) instruction is for reading out the old style of 8 - bit electronic signature, whose values are shown as table of id definitions. the rdid instruction code is followed by three dummy bytes, each bit being latched - in on si during the rising sck edge . then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdid instruction is ended by ce# going high. the device id 7 - id0 outputs repeatedly if additional clock cycles are continuously sent on sck while ce# is at low. table 8 .3 product identification manufacturer id (mf7 - mf0) issi serial flash 9dh instruction abh, 90h 9fh device id (id7 - id0) (id15 - id0) 64 mb 1 6 h 601 7 h 32mb 15h 6016h figure 8 .4 0 read product identification sequence figure 8 . 4 1 read product identification sequence (qpi)
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 50 rev. 0a 4/03/2014 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 1 1 7 1 6 4 0 c e # s c k i o 0 2 0 1 3 5 1 i o 1 1 2 2 2 1 8 1 4 6 2 2 3 1 9 1 5 7 3 i o 2 i o 3 1 1 1 0 9 8 c 4 c 5 c 6 c 7 c 0 c 1 c 2 c 3 m o d e 3 m o d e 0 d e v i c e i d 1 3 d u m m y b y t e s d e v i c e i d 1
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 51 rev. 0a 4/03/2014 8.25 read pro duct identification by jedec id operation (rdjdid, 9fh) the jedec id read instruction allows the user to read the manufacturer and product id of devices. refer to table 8 .3 product identification for manufacturer id and device i d. after the jedec id r ead command (9fh in spi mode, afh in qpi mode) is input, the manufacturer id is shifted out msb first followed by the 2 - byte electronic id (id15 - id0), one bit at a time. each bit is shifted out during the falling edge of sck. if ce# stays low after the last bit of the 2 - byte electronic id, the manufacturer id and 2 - byte electronic id will loop until ce# is pulled high . . figure 8 . 4 2 read product identification by jedec id read sequence figure 8 .4 3 rdidq command ( read id in qpi mode ) operation sck ce # si instruction 1001 1111 b 0 8 15 23 24 31 7 16 high impedance so capacity (id7 - id0) memory type (id15 - id - 8) manufacture id (mf7 - mf0) manufacture id (mf7 - mf0) memory type (id15 - id - 8) capacity (id7 - id0) 0 1 2 3 c e # s c k i o [ 3 : 0 ] a f h 7 : 4 3 : 0 m a n u f a c t u r e r i d 1 c o m m a n d 4 5 6 7 7 : 4 3 : 0 7 : 4 3 : 0 d e v i c e i d 1 d e v i c e i d 2
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 52 rev. 0a 4/03/2014 8.26 read de vice manufacturer and device id operation (rdmdid, 90h) the read product identification (rdid) instruction allows the user to read the manufacturer and product id of the devices. refer to table 8 .3 product identification for manufacturer id and device id. the rdid instruction code is followed by two dummy bytes and one byte address (a7~a0), each bit being latched - in on si during the rising edge of sck. if one byte address is initially set to a0 = 0, then the manufacturer id (9dh) is shifted out on so with the msb first followed by the device id 7 - id0. each bit shifted out during the falling edge of sck. if one byte address is initially set to a0 = 1, then d evice id 7 - id0 will be read first followed by the m anufacture id (9dh) . the manufacture and dev ice id can be read continuously alternating between the two until ce# is driven high. figure 8 . 4 4 read product identification by rdmdid read sequence manufacture id ( mf7 - mf0) device id (id7 - id0) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 . . . i n s t r u c t i o n = 1 0 0 1 0 0 0 0 b . . . 2 3 2 2 2 1 3 2 1 a 0 3 - b y t e a d d r e s s c e # s c k s i o s o h i g h i m p e d a n c e 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 7 6 5 4 3 2 1 0 c e # s c k s i o s o 6 5 4 3 2 1 7 0 d a t a o u t 1 d a t a o u t 2 3 1
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 53 rev. 0a 4/03/2014 note 1. (1) address a0 = 0, will output the 1 - byte manufacture id (mf7 - mf0) - > 1 - byte device (id7 - id0) address a0 = 1, will output the 1 - byte device (id7 - id0) - > 1 - byte manufacture id (mf7 - mf0) (2) the manufacture and device id can be read continuously and will alternate from one to the other until ce# pin is pulled h igh. manufacture id (mf7 - mf0) 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 s c k s i o s o 6 5 4 3 2 1 7 0 d a t a o u t 3 c e # 4 7
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 54 rev. 0a 4/03/2014 8.27 read unique id numbe r (rduid, 4b h) the read unique id number (rduid) instruction accesses a factory - set read - only 16 - byte number that is unique to the device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the rduid instruction is instated by driving the ce# pin low and shifting the instruction code (4bh) followed by 3 address bytes and a dummy byte. after which, the 16 - b yte id is shifted out on the falling edge of clk as shown below. note : the last byte of data will repeat when as the data will be read continuously. figure 8.45 rduid command operation table 8.4 unique id addressing a[23:16] a[15:9] a[8:4] a[3:0] xxh xxh 00h 0h byte address xxh xxh 00h 1h byte address xxh xxh 00h 2h byte address xxh xxh 00h xxh xxh 00h fh byte address d u m m y b y t e 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t 4 2 4 3 4 4 4 5 4 6 4 7 h i g h i m p e d a n c e 0 i n s t r u c t i o n = 4 b h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 . . . . . .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 55 rev. 0a 4/03/2014 8.28 read sfdp operation ( rdsfdp, 5ah) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is same as fast_read: ce# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use ce# to high at any time during data out. figure 8 . 4 6 rdsfdp command ( read sfdp ) operation d u m m y b y t e 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t 4 2 4 3 4 4 4 5 4 6 4 7 h i g h i m p e d a n c e 0 i n s t r u c t i o n = 5 a h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 . . . . . .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 56 rev. 0a 4/03/2014 table 8 .4 sfdp (serial flash discoverable parameters) definition table address (byte) data (hex) data (binary) description comment 00h 53h 0101 0011 sfdp signature fixed : 50444653h 01h 46h 0100 0110 02h 44h 0100 0100 03h 50h 0101 0000 04h 00h 0000 0000 sfdp minor revision number rev 1.0 05h 01h 0000 0001 sfdp major revision number 06h 00h 0000 0000 number of parameter numbers 1 parameter header 07h ffh 1111 1111 reserved 08h 00h 0000 0000 jedec specified jedec specified=00h 09h 00h 0000 0000 parameter table minor revision number rev 1.0 0ah 01h 0000 0001 parameter table major revision number 0bh 09h 0000 1001 parameter table length 9 dwords 0ch 30h 0011 0000 jedec parameter table pointer (ptp) point = 000030h 0dh 00h 0000 0000 0eh 00h 0000 0000 0fh ffh 1111 1111 reserved 10h 9dh 1001 1101 manufacturer id 11h 00h 0000 0000 reserved 12h 01h 0000 0001 reserved 13h 09h 0000 1001 reserved 14h 60h 0110 0000 issi parameter table pointer (ptp) point = 000060h 15h 00h 0000 0000 16h 00h 0000 0000 17h ffh 1111 1111 reserved
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 57 rev. 0a 4/03/2014 address (byte) data (hex) data (binary) description comment 30h 7 d h 0001 bit[01:00 ]: block/sector erase 00=reserved 01=4kb erase 10=reserved 11=not support 4k erase supports 4k sector erase 0001 bit[2] : write granularity 0:1byte ,1:64byte or larger granularity is 64byte or larger 0001 bit[3] : write enable instruction required for writing to non - volatile status registers 0 : not required 1 : required required 0001 bit[4] : write enable opcode select for writing to non - volatile status registers 0 : use 50h opcode 1 : use 06h opcode use 01h opcode 111 bit[7:5] : reserved 31h d7h/20h 1101 0111 or 0010 0000 sector erase op code (4kb) 32h 3f h 0001 bit[0] : reserved 0001 bit[1] : (1 - 1 - 2) fast read 0=not supported 1=supported supported 000 1 bit[1] : (1 - 1 - 4) fast read 0=not supported 1=supported supported 0001 bit[2] : (1 - 4 - 4) fast read 0=not supported 1=supported supported 0001 bit[3] : (1 - 2 - 2) fast read 0=not supported 1=supported supported 0001 bit[4] : double transfer rate (dtr) 0=not supported 1=supported supported 0000 0000 bit[6:5] : address bytes number type 00 : 3bytes only, 01 : 3 or 4 byte, 10 : 4byte only, 11 : reserved 3 bytes only 33h ffh 1111 1111 reserved address (byte) data (hex) data (binary) description comment
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 58 rev. 0a 4/03/2014 address (byte) data (hex) data (binary) description comment 34h ffh 1111 1111 64mb = 03ff ffff 32mb = 01ff ffff 35h ffh 1111 1111 36h ffh 1111 1111 37h 03h (64mb) or 01h (32mb) 0000 0111 38h 44h 0100 bit[4:0] : (1 - 4 - 4)fast read number of dummy cycles 0 0000b : dummy cycles not supported 4 dummy cycles 0100 bit[7:5] : (1 - 4 - 4)fast read number of mode bits 000b : mode bits not support 4 mode bits 39h ebh 1110 1011 (1 - 4 - 4) fast read opcode 3ah 00h 1000 bit[4:0] : (1 - 1 - 4)fast read number of dummy cycles 0 0000b : dummy cycles not support 8 dummy cycles supported 0000 bit[7:5] : (1 - 1 - 4)fast read number of mode bits 000b : mode bits not support mode bits not supported 3bh 00 h 0 00 0 0 0 00 (1 - 1 - 4) fast read opcode 3ch 00h 0 000 bit[4:0] : (1 - 1 - 2)fast read number of dummy cycles 0 0000b : dummy cycles not support d ummy cycles not supported 0000 bit[7:5] : (1 - 1 - 2)fast read number of mode bits 000b : mode bits not support mode bits not supported 3dh 3bh 0011 1011 (1 - 1 - 2) fast read opcode 3eh 04h 0100 bit[4:0] : (1 - 2 - 2)fast read number of dummy cycles 0 0000b : dummy cycles not support 4 dummy cycles 0000 bit[7:5] : (1 - 2 - 2)fast read number of mode bits 000b : mode bits not support mode bits not supported 3fh bbh 1011 1011 (1 - 2 - 2) fast read opcode 40h eeh 0000 bit[0] : (2 - 2 - 2) fast read 0=not supported 1=supported not supported 111 bit[3:1] : reserved 0000 bit[4] : (4 - 4 - 4) fast read 0=not supported 1=supported not supported 111 bit[7:5] : reserved 41h ffh 1111 1111 reserved 42h ffh 1111 1111 reserved
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 59 rev. 0a 4/03/2014 address (byte) data (hex) data (binary) description comment 43h ffh 1111 1111 reserved 44h ffh 1111 1111 reserved 45h ffh 1111 1111 reserved 46h 00h 0000 bit[4:0] : (2 - 2 - 2)fast read number of dummy cycles 0 0000b : dummy cycles not support dummy cycles not supported 0000 bit[7:5] : (2 - 2 - 2)fast read number of mode bits 000b : mode bits not support mode bits not supported 47h ffh 1111 1111 (2 - 2 - 2) fast read opcode 48h ffh 1111 1111 reserved 49h ffh 1111 1111 reserved 4ah 44h 0100 bit[4:0] : (4 - 4 - 4)fast read number of dummy cycles 0 0000b : dummy cycles not support 4 dummy cycles supported 0100 bit[7:5] : (4 - 4 - 4)fast read number of mode bits 000b : mode bits not support 4 mode bits supported 4bh ebh 1110 1011 (4 - 4 - 4) fast read opcode 4ch 0ch 0000 1100 sector type 1 size (4kb) 4dh 20h 0010 0000 sector type 1 opcode 4eh 0fh 0000 1111 sector type 1 size (32kb) 4fh 52h 0101 0010 sector type 1 opcode 50h 10h 0001 0000 sector type 1 size (64kb) 51h d8h 1101 1000 sector type 1 opcode 52h 00h 0000 0000 sector type 1 size (256kb) C not support 53h ffh 1111 1111 sector type 1 opcode 61h:60h 3600h 0 0 11 0110 0000 0000 vcc supply maximum voltage 2000h = 2.00v 2700h = 2.70v 3600h = 3.60v 3.60v
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 60 rev. 0a 4/03/2014 address (byte) data (hex) data (binary) description comment 63h:62h 2300h 0010 0011 0000 0000 vcc supply minimum voltage 1650h = 1.65v 2300h = 2.30v 2700h = 2.70v 2.30v 65h:64h b99eh 0000 bit[0] : hw reset# pin 0=not supported 1=supported not supported 0001 bit[1] : hw hold# pin 0=not supported 1=supported supported 0001 bit[2] : deep power down mode 0=not supported 1=supported supported 0001 bit[3] : sw reset 0=not supported 1=supported supported 1001 1001 bit[11:04] : sw reset opcode :99h 0001 bit[12] : power suspend / resume 0=not supported 1=supported supported 0001 bit[13] : erase suspend / resume 0=not supported 1=supported supported 0000 bit[14] : reserved 0001 bit[15] : wrap - around read mode 0=not supported 1=supported supported 66h c0h 1100 0000 wrap - around read mode opcode 67h 64h 0110 0100 wrap - around read data length 08h=support 8b wrap - around read 16h=support 8b & 16b 32h=support 8b &16b & 32b 64h=support 8b & 16b & 32b & 64b supports 8, 16, 32 or 64 byte wrap - around read
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 61 rev. 0a 4/03/2014 address (byte) data (hex) data (binary) description comment 69h:68h c8dbh 0001 bit[0] : individual block lock 0=not supported 1=supported supported 0001 bit[1] : individual block lock bit 0=not supported 1=supported supported 0011 0110 bit[09:02] : individual block lock opcode : 36h 0000 bit[10] : individual block lock bit default status 0=not supported 1=supported not supported 1000 bit[11] : secured programmable area 0=not supported 1=supported supported 0000 bit[12] : read lock 0=not supported 1=supported not supported 0000 bit[13] : permanent lock 0=not supported 1=supported not supported 0001 0001 bit[15:14] : reserved 6ah ffh 1111 1111 reserved 6bh ffh 1111 1111 reserved
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 62 rev. 0a 4/03/2014 8.29 no operation (nop , 00h ) the no operation command only cancels a reset enable command. nop has no impact on any other command. it can use in the spi and qpi mode. to execute a nop, the host drives ce# low, sends the nop command cycle (00h), then drives ce# high. 8.30 s oftware r eset (r eset - e nable (rsten , 66h ) and reset (rst , 99h ) the reset operation is used as a system (software) reset that puts the device in normal operating mode. this operation consists of two commands: reset - enable (rsten) and reset (rst). the reset operation requires the reset - enable command followed by the reset command. any command other than the reset command after the reset - enable command will disable the reset - enable. execute the ce# pin low ? sends the reset - enable command (66 h ), and drives ce# high. nex t, the host drives ce# low again, sends the reset command (99 h ), and drives c e # high. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 63 rev. 0a 4/03/2014 figure 8 . 4 7 software reset enable, software res et operation s ( rsten, 66h + rst, 99h ) 8.31 mode rese t operation (rstm, ffh) the mode reset command is used to conclude subsequent frdio and frqio operations. it resets the mode bits to a value that is not ax. it should be executed after an frdio or frqio operation, and is recommended also as the first command after a system rese t. the timing sequence is different depending whether the mr command is used after an frdio or frqio, as shown in figure 8 . 4 8 figure 8 . 4 8 mode reset command 1 4 1 5 i n s t r u c t i o n = 0 1 1 0 0 1 1 0 b c e # s c k s i o s o h i g h i m p e d a n c e i n s t r u c t i o n = 1 0 0 1 1 0 0 1 b 1 2 1 3 1 0 1 1 8 9 6 7 4 5 2 3 0 1 i n s t r u c t i o n = 1 1 1 1 1 1 1 1 b c e # s c k s i o s o h i g h i m p e d a n c e m o d e r e s e t f o r q u a d i / o m o d e r e s e t f o r d u a l i / o i n s t r u c t i o n = 1 1 1 1 1 1 1 1 b 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 64 rev. 0a 4/03/2014 8.32 security information row the security information row is comprised of an additional 4 x 256 bytes of programmable information . the security bits can be reprogrammed by the user. any program security instruction issued while an erase, program or write cycle is in progress is reject ed without having any effect on the cycle that is in progress. table 8 .5 information row address address assignment a [23:16] a [15:8] a[7:0] irl0 (information row lock0) 00h 00h byte address irl1 00h 10h byte address irl2 00h 20h byte address irl3 00h 30h byte address bit 7~4 of the function register is used to permanently lock the programmable memory array. when function register bit irlx = 0 , the 256 bytes of the programmable memory array can be programmed. when function register bit irlx = 1 , the 256 bytes of the programmable memory array function as read only . 8.33 information row erase operation ( irer, 64h) information row erase instruction erases the information row x (x : 0~3) array , the write enable latch (wel) must be set via a write enable (wren) instruction. the wel bit is reset automatically after the completion of sector an erase operation. a i r er instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence the ir er instruction code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase voltage and timing. refer to figure 8 . 4 9 for ir er sequence. figure 8 . 4 9 i r er command ( information row erase ) operation 0 i n s t r u c t i o n = 6 4 h 2 3 c e # s c k s i 3 s o 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 2 1 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 65 rev. 0a 4/03/2014 8.34 information row prog ram operation ( irp, 62h) the information row program ( ir p ) instruction allows up to 1024 bytes, 4x 256 bytes , data to be programmed into memory in a single operation. before the execution of pp instruction, the write enable latch (wel) must be enabled through a write enable (wren) instruction. the i r p instruction code, three address bytes and program data (1 to 256 bytes) are input via the sl line. program operation will sta rt immediately after the ce# goes high, otherwise the i r p instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program ope ration can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 1024 bytes data are sent to a device, the address counter rolls over within the same page . t he previously latched data are discarded and the last 1024 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note : a program operation can alt er 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 8 . 50 irp command ( information row program ) operation 0 i n s t r u c t i o n = 6 2 h 2 3 c e # s c k s i 3 s o 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 2 0 7 5 7 6 5 2 1 0 2 0 7 6 2 0 7 7 2 0 7 8 2 0 7 9 4 3 2 1 0 1 s t b y t e d a t a - i n 2 5 6 t h b y t e d a t a - i n
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 66 rev. 0a 4/03/2014 8.35 information row read operation ( irrd, 68h) the i rrd instruction is used to read memory data at up to a 1 33 mhz clock. the irrd instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bit shifted out at a maximum frequency f ct , during the falling edge of sck. the address is au tomatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single irrd instruction. the irrd instruction is te rminated by driving ce# high (vih). if a irrd instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 8 . 5 1 irrd command ( information row read ) operation d u m m y b y t e 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t 4 2 4 3 4 4 4 5 4 6 4 7 h i g h i m p e d a n c e 0 i n s t r u c t i o n = 6 8 h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 . . . . . .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 67 rev. 0a 4/03/2014 8.36 fast read dtr mode operation (f rdtr, 0dh) the frdtr instruction is for doubling reading data out, signals are triggered on both rising and falling edge of clock. the address is latched on both rising and falling edge of sck, and data of each bit shifts out on both rising and falling edge of sck at a maximu m frequency f c 2 . the 2 - bit address can be latched - in at one clock, and 2 - bit data can be read out at one clock, which means one bit at rising edge of clock, the other bit at falling edge of clock. the first address byte can be at any location. the address is automatical ly increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single frdtr instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing frdtr ins truction is: ce# goes low sending frdtr instruction code (1bit per clock) 3 - byte address on si (2 - bit per clock) 6 - dummy clocks (default) on si data out on so (2 - bit per clock) to end frdtr operation can use ce# to high at any time during data ou t. (please refer to figure 8 . 5 2 ) while program/erase/write status register cycle is in progress, frdtr instruction is rejected without any im - pact on the program/erase/write status register current cycle. note: mode 0 is not supported in dtr operation figure 8 . 5 2 frdtr command ( fast read dtr mode ) operation note : number of dummy cycles depends on clock speed. detailed information in table 6.9 . read dummy cycles 0 7 8 1 9 2 3 2 4 2 5 2 6 2 7 c e # s c k s i 0 d h 4 d u m m y c y c l e s s o a 2 3 a 2 3 a 1 a 0 1 2 a d d r e s s c y c l e s d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d a t a 1 d a t a 2
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 68 rev. 0a 4/03/2014 8.37 fast read d ual io dtr mode operation (f rddtr, bdh) the frddtr instruction enables double transfer rate throughput on dual i/o of serial flash in read mode. the ad dress (interleave on dual i/o pins) is latched on both rising and falling edge of sck, and data (interleave on dual i/o pins) shift out on both risi ng and falling edge o f sck at a maximum frequency f t2 . the 4 - bit address can be latched - in at one clock, and 4 - bit data can be read out at one clock, which means two bits at rising edge of clock, the other two bits at falling edge of clock. the first addre ss byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single frddtr instruction. the address counter rolls over to 0 when the highest ad dress has been reached. once writing frddtr instruction, the following address/dummy/ data out will perform as 4 - bit instead of previous 1 - bit. the sequence of issuing frddtr instruction is: ce# goes low sending frddtr instruction (1 - bit per clock) 24 - bit address interleave on sio1 & sio0 (4 - bit per clock) 6 - bit dummy clocks on sio1 & sio0 data out inter leave on sio1 & sio0 (4 - bit per clock) to end frddtr operation can use ce# to high at any time during data out (please refer to figure 8 . 5 3 for 2 x i/o double transfer rate read mode timing waveform). while program/erase/write status register cycle is in progress, frddtr instruction is rejected without any impact on the program/erase/write status register current cycle. note: mode 0 is not s upported in dtr operation figure 8 . 5 3 frddtr command ( fast read dual io dtr mode ) operation note : number of dummy cycles depends on clock speed. detailed information in table 6.9 . read dummy cycles 0 7 8 1 3 1 7 1 8 1 9 2 0 2 1 c e # s c k s i b d h 4 d u m m y c y c l e s s o a 2 2 a 2 0 a 2 a 0 6 a d d r e s s c y c l e s d 7 d 5 d 3 d 1 d 7 d 5 d 3 d 1 d 7 d a t a 1 d a t a 2 a 2 1 a 3 a 0 d 4 d 2 d 0 d 6 d 4 d 2 a 1 a 2 3 6 4 7 5 m o d e b i t s d 6 d 0 d 6 d a t a 3
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 69 rev. 0a 4/03/2014 8.38 fast read quad io dtr m ode operation (f rqdtr, edh) the frqdtr instruction enables double transfer rate throughput on quad i/o of serial flash in read mode. a quad enable (qe) bit of status register must be set to "1" before sending the frqdtr instruction. the address (interleave on 4 i/o pins) is latched on both rising and falling edge of sck, and data (interleave on 4 i/o pins) shift out on both rising and falling edge o f sck at a maximum frequency f q2 . the 8 - bit address can be latched - in at one clock, and 8 - bit data can be read out at one clock, which means four bits at rising edge of clock, the other four bits at fall ing edge of clock. the first address byte can be at any location. the address is automatically increased to the next higher a ddress after each byte data is shifted out, so the whole memory can be read out at a single frqdtr instruc tion. the address counter rolls over to 0 when the highest address has been reached. once writing frqdtr instruc tion, the following address/dummy/da ta out will perform as 8 - bit instead of previous 1 - bit. the sequence of issuing frqdtr instruction is: ce# goes low sending frqdtr instruction (1 - bit per clock) 24 - bit address interleave on sio3, sio2, sio1 & sio0 (8 - bit per clock) 8 dummy clocks d ata out interleave on sio3, sio2, sio1 & sio0 (8 - bit per clock) to end frqdtr operation can use ce# to hi gh at any time during data out. another sequence of issuing enhanced mode of frqdtr instruction especially useful in random access is: ce# goes low sending frqdtr instruction (1 - bit per clock) 3 - bytes address interleave on sio3, sio2, sio1 & sio0 (8 - bit per clock) performance enhance toggling bit p[7:0] 7 dummy clocks data out(8 - bit per clock) still ce# goes high ce# goes low (eliminate 4 r ead instruction) 24 - bit random access a ddress (please refer to figure 8. 5 4 for 4x i/o double transfer rate read enhance performance mode timing waveform). while program/erase/write status register cycle is in progress, frqdtr instruction is rejected without any impact on the program/erase/write status register current cycle. figure 8 . 5 4 frqdtr command ( fast read quad io dtr mode ) operation note : number of dummy cycles depends on clock speed. detailed information in table 6.9 . read dummy cycles 0 7 8 1 0 1 4 1 5 1 6 c e # s c k i o 0 e d h 4 d u m m y c y c l e s i o 1 a 2 0 a 1 6 a 4 a 0 3 a d d r e s s c y c l e s d 5 d 1 d 5 d 1 d 5 d a t a 1 d a t a 2 a 1 7 d 0 d 4 d 0 d 4 a 1 a 2 1 m o d e b i t s d 4 i o 2 d 6 d 2 d 6 d 2 d 6 a 1 8 a 2 a 2 2 i o 3 d 7 d 3 d 7 d 3 d 7 a 1 9 a 3 a 2 3 a 1 2 a 8 a 9 a 1 3 a 1 0 a 1 4 a 1 1 a 1 5 a 5 a 7 a 6 4 5 6 7
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 70 rev. 0a 4/03/2014 8.39 sector lock/unlock f unction s sector unlock operation (secunlock, 26h) the sector unlock command allows the user to select a specific sector to allow program and erase operations. this instruction is effective when the blocks are designated as write - protected through the bp0, bp1, bp2 and bp3 bits in the status register. only one sector can be enabled at any time. to enable a different sector, a previously enabled sector must be disabled by executing a sector lock command. the instruction code is followed by a 24 - bit address specifying the target sector, but a0 through a11 are not decoded. the remaining sectors within the same block remain in read - only mode. s ec to r u n l o ck s e qu e n ce in the sector unlock procedure, [ a11:a0 ] need to be 0 , in order for the unlock procedure to be completed, the chip will regard anything else as an illegal command. note: 1. if the number of c l o c k cycles do n ot m at c h 8 cycles ( c o m m and ) + 24 c l o c k s ( add r e ss) , the command will be ignored . 2. wren ( 0 6h) must be executed b e f o r e s e c tor u n l o c k i n s t r u c t i on s. 0 i n s t r u c t i o n = 6 4 h 2 3 c e # s c k s i 3 s o 3 - b y t e a d d r e s s 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 h i g h i m p e d a n c e 2 2 2 1 . . . 2 1 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 71 rev. 0a 4/03/2014 sector lock operation (seclock, 24h) t he s e c tor lo c k c o mm and r e v e rs es t h e f un c t i o n of the s e c tor u n l o c k c o m m a n d. t he i n s t r u c t i on c ode does n ot r e q u i r e an add r e s s to be s p e c i f i ed, as o n l y one s e c tor c a n b e e n a b l ed at a t i m e. t he r e m a i n i n g s e c to r s w i th i n t h e s a m e b l o c k r e m a i n i n r ead - o n l y m ode. s e c to r lo c k se qu e n ce i n s t r u c t i o n = 2 4 h c e # s c k s i o s o h i g h i m p e d a n c e 0 1 2 3 4 5 6 7
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 72 rev. 0a 4/03/2014 9. electrical characteristics 9 .1 absolute maximum rat ings (1) storage temperature - 5 5 o c to +1 30 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead - free package 260 o c 3 seconds input voltage with respect to ground on all pins - 0.5v to v cc + 0.5v all output voltage with respect to ground - 0.5v to v cc + 0.5v v cc - 0.5v to +6.0v notes : 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . 9. 2 operating range part number is25 lp 032/064 operating temperature ( extended grade) - 4 0 o c to 1 0 5 o c operating temperature (automotive grade a1) - 40c to 85 c operating temperature (automotive grade a2) - 40c to 1 05 c operating temperature (automotive grade a3) - 40c to 125c vcc power supply 2.3 v C 9. 3 dc characteristics (under operating range) symbol parameter condition min typ max units i cc1 v cc active read current v cc = 3.6 v at 50 mhz, so = open 10 15 ma i cc2 v cc program/erase current v cc = 3.6 v at 50 mhz, so = open 25 4 0 ma i sb1 v cc standby current cmos v cc = 3.6 v, ce# = v cc 50 i sb2 v cc standby current ttl v cc = 3.6 v, ce# = v ih to v cc 3 ma i li input leakage current v in = 0v to v cc 1 i lo output leakage current v in = 0v to v cc , t ac = 0 o c to 135 o c 1 v il (1) input low voltage - 0.5 0. 3 v cc v v ih (1) input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage 2.3 v < v cc < 3.6 v i ol = 100 a 0. 2 v v oh output high voltage i oh = - v cc - 0.2 v note 1. maximum dc voltage on input or i/o pins is v cc + 0.5v. during voltage transitions, input or i/o pins may overshoot v cc by + 2.0 v for a period of time not to exceed 20ns. minimum dc voltage on input or i/o pins is - 0.5 v. during voltage transitions, input or i/o pins may undershoot gnd by - 2.0 v for a period of time not to exceed 20ns.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 73 rev. 0a 4/03/2014 9. 4 ac m easurement c onditions symbol parameter min max units cl load capacitance up to 104 mhz 30 pf cl load capacitance up to 133 mhz 15 pf tr,tf input rise and fall times 5 ns vin input pulse voltages 0.2v cc to 0.8v cc v vrefi input timing reference voltages 0.3v cc to 0.7v cc v vrefo output timing reference voltages 0.5v cc v figure 9. 1 output test load & ac measurement i/o waveform o u t p u t p i n 1 . 8 k 1 . 2 k 1 5 / 3 0 p f 0 . 8 v c c 0 . 2 v c c i n p u t v c c / 2 a c m e a s u r e m e n t l e v e l
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 74 rev. 0a 4/03/2014 9. 5 ac characteristics (under operating range, refer to section 9. 4 for ac measurement conditions ) symbol parameter min typ max units f ct clock frequency for fast read mode 0 1 33 mhz f c clock frequency for read mode 0 50 mhz f c 2 clock frequency for fast read dtr mode 0 66 mhz f t2 clock frequency for fast read dual i/o dtr mode 0 66 mhz f q2 clock frequency for fast read quad i/o dtr mode 0 66 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 7 ns t cs ce# setup time 5 ns t ch ce# hold time 5 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t v output valid @ 133 mhz 7 ns output valid @ 104 mhz 8 ns t oh output hold time normal mode 2 ns t dis output disable time 8 ns t hd output hold time 2 ns t hlch hold active setup time relative to sck 5 ns t chhh hold active hold time relative to sck 5 ns t hhch hold not active setup time relative to sck 5 ns t chhl hold not active hold time relative to sck 5 ns t lz hold to output low z 12 ns t hz hold to output high z 12 ns t ec secto r erase time 50 150 ms block erase time (32kbyte) 0.25 0.75 s block erase time (64kbyte) 0.5 1.5 s chip erase time ( 032 mb) 45 90 s t pp page program time 0. 3 1. 0 ms t vc e vcc(min) to ce# low 1 m s t res1 release deep power down 3 s t dp deep power down 3 s t w write status register time 10 15 ms t sus suspend to read ready 100 s t srst software reset cover time 20 100 s
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 75 rev. 0a 4/03/2014 9. 6 serial input/output timing (1) figure 9. 2 serial input/output timing note 1. for spi mode 0 (0,0) figure 9. 3 hold timing h i - z s o s i s c k c e # v i h v i l v i h v i l v i h v i l v o h v o l v a l i d i n t c s t c k h t c k l t d s t d h t c h t c e h t v t d i s h i - z t o h s i s o s c k c e # h o l d # t c h h l t h l c h t c h h h t h h c h t h z t l z
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 76 rev. 0a 4/03/2014 9. 7 power - up and power - down at power - up and power - down, the device must be not selected until vcc reaches at the right level. ( adding a simple pull - up resistor on ce# is recommended. ) power up timing symbol parameter min. max unit tvce (1) vcc(min) to ce# low 1 m s tpuw (1) power - up time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 2.1 v note1. these parameters are characterized and are not 100% tested. 9. 8 program/erase perfor mance parameter unit typ max sector erase time ms 50 200 block erase time 32kbyte s 0.25 0.75 block erase time 64kbyte s 0.5 1.5 chip erase time ( 032 mb) s 45 90 page programming time ms 0. 3 1. 0 byte program s tbd tbd note : these parameters are characterized and are not 100% tested. v c c v c c ( m a x ) v c c ( m i n ) v ( w r i t e i n h i b i t ) r e s e t s t a t e t v c e t p u w r e a d a c c e s s a l l o w e d d e v i c e f u l l y a c c e s s i b l e c h i p s e l e c t i o n n o t a l l o w e d a l l w r i t e c o m m a n d s a r e r e j e c t e d
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 77 rev. 0a 4/03/2014 9. 9 reliability characteristics parameter min unit test method endurance 1 00,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd C human body model 2,000 volts jedec standard a114 esd C machine model 200 volts jedec standard a115 latch - up 100 + icc1 ma jedec standard 78 note : these parameters are characterized and are not 100% tested.
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 78 rev. 0a 4/03/2014 10. p ackage type information 10 . 1 8 - pin jedec 208mil bro ad small outline integrated c ircuit (soic) packag e (jb) (1) note1. all dimensions are in millimeters. 5 . 3 8 5 . 1 8 5 . 3 8 5 . 1 8 8 . 1 0 7 . 7 0 t o p v i e w 1 . 2 7 b s c 0 . 4 8 0 . 3 5 0 . 2 5 0 . 0 5 2 . 1 6 1 . 7 5 s i d e v i e w 0 . 8 0 0 . 5 0 0 . 2 5 0 . 1 9 e n d v i e w 5 . 3 3 5 . 1 3 5 . 3 8 5 . 1 8
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 79 rev. 0a 4/03/2014 10 .2 8 - contact ultra - thin small outline n o - lead (wson) package 6x5mm (jk) (1) note1. all dimensions are in millimeters. 5 . 0 0 b s c 6 . 0 0 b s c t o p v i e w s i d e v i e w 0 . 2 5 0 . 1 9 0 . 8 0 0 . 7 0 b o t t o m v i e w p i n 1 4 . 0 0 3 . 4 0 0 . 4 8 0 . 3 5 1 . 2 7 b s c 0 . 7 5 0 . 5 0
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 80 rev. 0a 4/03/2014 10 .3 8 - contact ultra - thin small outline n o - lead (wson) package 8x6mm (jl) (1) . s y m b o l d i m e n s io n in m m m i n. n o m m a x a 0 . 70 0 . 7 5 0 .80 a 1 0.00 0. 0 2 0.05 a 2 - - - 0 . 2 0 - - - d 7 . 90 8 . 0 0 8 . 10 e 5 . 90 6 . 0 0 6 . 10 d1 4.65 4. 7 0 4.75 e1 4.55 4. 6 0 4.65 e - - - 1 . 2 7 - - - b 0 . 35 0 . 4 0 0 . 48 l 0.4 0. 5 0 0.60 note1. all dimensions are in millimeters .
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 81 rev. 0a 4/03/2014 10 . 4 8 - pin 208mil vsop package (jf) (1) symbols min typ max a - - 1 a1 0.05 0.1 0.15 a2 0.75 0.8 0.85 b 0.35 0.42 0.48 c - .127 ref - d 5.18 5.28 5.38 e 7.7 7.9 8.1 e1 5.18 5.28 5.38 e - 1.27 - l 0.5 0.65 0.8 y - - 0.1 0 - 8 note1. all dimensions are in millimeters. l e b a a 2 a 1 c d 1 0 ( 4 x ) e 1 e
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 82 rev. 0a 4/03/2014 10 . 5 16 - lead plastic small outline package (300 mils body width ) (jm) (1) note1. all dimensions are in millimeters. 1 . 2 7 0 . 5 1 0 . 3 3 2 . 4 2 . 2 5 2 . 3 5 2 . 6 5 0 . 1 8 0 0 0 1 . 2 7 0 . 4 d e t a i l a d e t a i l a 0 . 2 3 m i l l i m e t e r s 1 8 9 1 6 1 0 . 5 1 0 . 1 7 . 4 7 . 6 1 0 . 0 1 0 . 6 5 0 . 3 2 0 . 1 0 . 3
is25 l p032/064 integrated silicon solution, inc. - www.issi.com 83 rev. 0a 4/03/2014 11. o rdering information density frequency (mhz) order part number package 64mb 133 IS25LP064 - jble 8 - pin soic 208mil IS25LP064 - jkle 8 - pin wson (6x5 mm) IS25LP064 - jlle 8 - pin wson (6x8 mm) IS25LP064 - jfle 8 - pin vsop 208mil IS25LP064 - jmle 16 - pin 300mil IS25LP064 - jbla* 8 - pin soic 208mil (call factory) IS25LP064 - jkla* 8 - pin wson (6x5 mm) (call factory) IS25LP064 - jlla* 8 - pin wson (6x8 mm) (call factory) IS25LP064 - jfla* 8 - pin vsop 208mil (call factory) IS25LP064 - jmla* 16 - pin 300mil (call factory) IS25LP064 - jwle kgd (call factory) a* = a1, a2, a3 automotive temperature range e = - 40 to 105 c a1= - 40 to 85 c a2= - 40 to 105 c a3= - 40 to 125 c density frequency (mhz) order part number package 32mb 133 is25lp032 - jble 8 - pin soic 208mil is25lp032 - jkle 8 - pin wson (6x5 mm) is25lp032 - jlle 8 - pin wson (6x8 mm) is25lp032 - jfle 8 - pin vsop 208mil is25lp032 - jmle 16 - pin 300mil is25lp032 - jbla* 8 - pin soic 208mil (call factory) is25lp032 - jkla* 8 - pin wson (6x5 mm) (call factory) is25lp032 - jlla* 8 - pin wson (6x8 mm) (call factory) is25lp032 - jfla* 8 - pin vsop 208mil (call factory) is25lp032 - jmla* 16 - pin 300mil (call factory) is25lp032 - jwle kgd (call factory)

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